There is a type of incrementer called a high frequency divider. In a high frequency divider, the values within the incrementer change in a predefined fashion, but not necessarily by a mathematical addition or subtraction. For example, 000000 could be the first state, 000001 could be the second state, 000011 could be the third, 000111 could be the fourth, 001111 could be the fifth, 011111 could be the sixth, 111111 could be the seventh, 011111 could be the eighth state, and so on. The values could represent the generation of a square wave, although other uses are also possible. The particular transition from state value to state value is a function of the internal logic of the high frequency divider.
However, there is a problem with typical high frequency dividers. One such problem is if the system starts up in an invalid state. In the example above, for instance, the state 010101 is not a desired state, but is physically accessible at start up. This can happen when a system first powers up, as the states of the latches within the system can be indeterminate. Alternatively, a catastrophic event, such as an electromagnetic pulse, for example, can disrupt the latches or other system components. If this happens, the high frequency divider can be forced into an undesired state.
Moreover, if left uncorrected in conventional systems, the states could cycle from one undesired state to another undesired state, without ever becoming a desired state and getting back on track. In some conventional systems, the system can be reset, and a preloaded “seed” state can be entered into the system. However, this is an expensive proposition, time-wise, and errors can creep in if the initial “seed” state is somehow inaccurate. Further, if an electromagnetic pulse changes the state within the circuit to an invalid state or sequence, this invalid state or sequence should be deleted, which costs additional time and circuitry area, and a system reset is issued, which also costs additional time.
Therefore, there is a need to ensure that a desired state is arrived at after a certain number of state transitions in a manner that addresses at least some of the problems associated with the prior art.